Why Kolabtree
Getting started is quick and easy. No upfront fees
It’s free to request a service and invite bids from experts
Discuss requirements with the expert in detail before accepting statement of work from Kolabtree
Collaborate with the expert directly to get your work done the right way
Fund project when you hire the expert, but approve the deliverables only once work is done
Want to hire this expert for a project? Request a quote for free.
Profile Details
Create Project
USD 300 /hr
Hire James S.
United States
USD 300 /hr
Profile Summary
Subject Matter Expertise
Work Experience

Senior Director R&D

Synopsys Inc

September 1995 - May 2017

Senior Manager, Semiconductor Design Engineering

Standard Microsystems Corporation (SMC)

September 1982 - September 1995


BS EE, Electrical Engineering

Rensselaer Polytechnic Institute

January 1978 - May 1982

  • Certification details not provided.
(2017). Method and apparatus for floating or applying voltage to a well of an integrated circuit. USPTO.
(2016). Placing transistors in proximity to through-silicon vias. USPTO.
(2015). ESD/antenna diodes for through-silicon vias. USPTO.
(2014). Determination of meta-stable latch bias voltages. USPTO.
(2013). Method and apparatus for placing transistors in proximity to through-silicon vias. USPTO.
(2004). Path dependent power modeling. USPTO.
(2004). Apparatus and method for improved precomputation to minimize power dissipation of integrated circuits. USPTO.
(2001). Method and system for pipe stage gating within an operating pipelined circuit for power savings. USPTO.
(2001). Three-dimensional power modeling table having dual output capacitance indices. USPTO.
(2000). Method and system for determining a signal that controls the application of operands to a circuit-implemented function for power savings. USPTO.
(1998). State dependent power modeling. USPTO.
(1988). Video dot intensity balancer. USPTO.
(1987). Virtual ground read only memory. USPTO.
(2004). A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals. International Test Conference, ITC 2004.
(2003). Test Pattern Compression Using Prelude Vectors in Fan-out Scan Chain with Feedback Architecture. Design Automation and Test in Europe Conference, DATE 2003.
(2002). Innovations in Test Automation. 20th IEEE VLSI Test Symposium, VTS 2002.
(2000). Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. Design Automation and Test in Europe, DATE 2000.
(1997). Low power design without compromise (panel). International Symposium on Low Power Electronics and Design, ISLPED 1997.
(1997). Low-power design tools—where is the impact? (panel). Design Automation Conference, DAC 1997.